AN-6754 Datasheet, PDF (3/8 Pages) Fairchild Semiconductor – Design Guideline to Replace SG6742

AN-6754
HV Startup Circuit
Figure 3 shows the simplified schematic for the HV startup
circuit. When the AC line is applied to the power supply,
the internal high-voltage current source charges the hold-up
capacitor, C₁, through a startup resistor, R_HV. As the V_DD
pin voltage reaches the turn-on threshold, V_DD-ON, the PWM
controller is enabled and starts normal operation. Then the
high-voltage current source is switched off and the supply
current is drawn from the auxiliary winding of the main
transformer, as shown in Figure 3. For better line surge
immunity of HV pin, it is typical to use a HV resistor larger
than 150kΩ. When large capacitor is required for V_DD, the
HV resistor limits the charging current for V_DD capacitor
increasing the startup time. In that case, a two-stage V_DD
capacitor circuit, as shown in Figure 3, is typically used.
APPLICATION NOTE
Under-Voltage Lockout (UVLO)
The FAN6754 has an under-voltage lockout for V_DD. Figure
5 shows the turn-on (V_DD-ON) and turn-off (V_DD-OFF)
threshold levels. It is worthwhile to notice that there is
another V_DD turn-off level (V_DD-OLP) to minimize the power
dissipation of the power stage during the overload
protection / open-loop protection condition by extending the
V_DD discharge time.
If output short is overloaded or the feedback loop is
opened, the FB voltage remains above V_FB-OLP for OLP
delay time (t_D-OLP) until the protection is triggered. During
that time, the MOSFET drain-to-source current reaches its
pulse-by-pulse current limit level for every switching cycle,
causing a large amount of power dissipation to the
switching devices and transformer. With the two-step
UVLO mechanism, the average input power during
overload or open-loop condition is greatly reduced.
I_DD
I_DD-OP
I_DD-OLP
Figure 3. Startup Circuit
Soft-Start
FAN6754 has an internal soft-start circuit that progressively
increases the pulse-by-pulse current limit level as shown in
Figure 4. The built-in soft-start circuit significantly reduces
the input current overshoot during startup, which also
minimizes output voltage overshoot.
I_DD-ST
V_DD-OLP
6.5V
V_DD-OFF
9V
V_DD
V_DD-
ON
16.5V
Figure 5. UVLO Specification
0.46
0.4
0.36
0.28
0.2
0.1
0.1
0.3 0.4 0.5
time (ms)
0.7
Figure 4. Pulse-by-Pulse Current Limit for Soft-Start
Figure 6. Two-Level UVLO
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/18/09
3
www.fairchildsemi.com