74ACT715 Datasheet, PDF (3/14 Pages) Fairchild Semiconductor – Programmable Video Sync Generator

Register Description
All of the data registers are 12 bits wide. Width’s of all
pulses are defined by specifying the start count and end
count of all pulses. Horizontal pulses are specified with-
respect-to the number of clock pulses per line and vertical
pulses are specified with-respect-to the number of lines per
frame.
REG0—STATUS REGISTER
B10—
B11—
Disable System Clock (0)
Enable System Clock (1)
Default values for B10 are “0” in the ACT715
and “1” in the ACT715-R.
Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for
internal testing only.
The Status Register controls the mode of operation, the
signals that are output and the polarity of these outputs.
The default value for the Status Register is 0 (000 Hex) for
the ACT715 and is “1024” (400 Hex) for the ACT715-R.
Bits 0–2
HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizon-
tal Sync and Blank pulses.
REG1— Horizontal Front Porch
B₂ B₁ B₀ VCBLANK VCSYNC HBLHDR
0 0 0 CBLANK CSYNC HGATE
(DEFAULT)
0 0 1 VBLANK CSYNC HBLANK
HSYNVDR
VGATE
VGATE
REG2—
REG3—
REG4—
Horizontal Sync Pulse End Time
Horizontal Blanking Width
Horizontal Interval Width # of Clocks
per Line
0 1 0 CBLANK VSYNC HGATE HSYNC VERTICAL INTERVAL REGISTERS
011
100
101
110
111
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
VSYNC
CSYNC
CSYNC
VSYNC
VSYNC
Bits 3–4
HBLANK
CUSOR
HBLANK
CUSOR
HBLANK
HSYNC
VINT
VINT
HSYNC
HSYNC
B₄ B₃
Mode of Operation
0 0 Interlaced Double Serration and
Equalization
(DEFAULT)
0 1 Non Interlaced Double Serration
1 0 Illegal State
1 1 Non Interlaced Single Serration and Equalization
The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical Blank
and Sync Pulses.
REG5— Vertical Front Porch
REG6— Vertical Sync Pulse End Time
REG7— Vertical Blanking Width
REG8—
Vertical Interval Width
per Frame
# of Lines
EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
These registers determine the width of equalization and
serration pulses and the vertical interval over which they
occur.
REG 9— Equalization Pulse Width End Time
REG10— Serration Pulse Width End Time
Double Equalization and Serration mode will output equal-
ization and serration pulses at twice the HSYNC frequency
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output
an equalization or serration pulse for every HSYNC pulse.
In Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even
field. Interlaced Single Equalization and Serration mode is
not possible with this part.
REG11—
REG12—
Equalization/Serration Pulse Vertical
Interval Start Time
Equalization/Serration Pulse Vertical
Interval End Time
VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Inter-
rupt signal if used.
Bits 5–8
Bits 5 through 8 control the polarity of the outputs. A value
of zero in these bit locations indicates an output pulse
active LOW. A value of 1 indicates an active HIGH pulse.
B5—
VCBLANK Polarity
B6—
VCSYNC Polarity
REG13— Vertical Interrupt Activate Time
REG14— Vertical Interrupt Deactivate Time
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating sig-
nals.
B7—
HBLHDR Polarity
REG15— Horizontal Cursor Position Start Time
B8—
HSYNVDR Polarity
REG16— Horizontal Cursor Position End Time
Bits 9–11
Bits 9 through 11 enable several different features of the
device.
REG17— Vertical Cursor Position Start Time
REG18— Vertical Cursor Position End Time
B9—
Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
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