FAN5400_11 Datasheet, PDF (28/37 Pages) Fairchild Semiconductor – FAN5400 / FAN5401 / FAN5402 / FAN5403 / FAN5404 / FAN5405 USB-Compliant Single-Cell Li-Ion Switching Charger

BST State
This is the normal operating mode of the regulator. The
regulator uses a minimum t_OFF-minimum t_ON modulation
scheme. The minimum t_OFF is proportional to ^VIN , which
V_OUT
keeps the regulator’s switching frequency reasonably
constant in CCM. t_ON(MIN) is proportional to V_BAT and is a
higher value if the inductor current reached 0 before t_OFF(MIN)
in the prior cycle.
To ensure the VBUS does not pump significantly above the
regulation point, the boost switch remains off as long as
FB > V_REF.
Boost Faults
If a BOOST fault occurs:
1. The STAT pin pulses.
2. OPA_MODE bit is reset.
3. The power stage is in High-Impedance Mode.
4. The FAULT bits (REG0[2:0]) are set per Table 18.
Restart After Boost Faults
If boost was enabled with the OPA_MODE bit and
OTG_EN=0, Boost Mode can only be enabled through
subsequent I²C commands since OPA_MODE is reset on
boost faults. If OTG_EN=1 and the OTG pin is still ACTIVE
(see Table 16), the boost restarts after a 5.2ms delay, as
shown in Figure 44. If the fault condition persists, restart is
attempted every 5ms until the fault clears or an I²C
command disables the boost.
VREG Pin
The VREG pin on FAN5400 - FAN5402 provides a voltage
protected from over-voltage surges on VBUS, which can be
used to run auxiliary circuits. This voltage is essentially a
current-limited replica of PMID. The maximum voltage on
this node is 5.9V.
FAN5403-FAN5405 provide a 1.8V regulated output on this
pin, which can be disabled through I²C by setting the
DIS_VREG bit (REG5[6]). VREG can supply up to 2mA. This
circuit, which is powered from PMID, is enabled only when
PMID > V_BAT and does not drain current from the battery.
During boost, V_REG is off. It is also off when the HZ_MODE
bit (REG1[1])=1.
Monitor Register (Reg10H)
Additional status monitoring bits enable the host processor
to have more visibility into the status of the IC. The monitor
bits are real-time status indicators and are not internally
debounced or otherwise time qualified.
The state of the MONITOR register bits listed in High-
Impedance Mode are only valid when V_BUS is valid.
Table 18. Fault Bits During Boost Mode
Fault Bit
B2 B1 B0
Fault Description
0 0 0 Normal (no fault)
0 0 1 V_BUS > VBUS_OVP
V_BUS fails to achieve the voltage required to
0
1
0
advance to the next state during soft-start
or sustained (>50s) current limit during the
BST state.
0 1 1 V_BAT < UVLO_BST
1 0 0 N/A: This code does not appear.
1 0 1 Thermal shutdown
1 1 0 Timer fault; all registers reset.
1 1 1 N/A: This code does not appear.
VBUS 0
560
450mA
BATTERY
CURRENT ₀
64
BOOST
ENABLED
5200
Figure 44. Boost Response Attempting to Start into V_BUS
Short Circuit (Times in s)
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
28
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