TMC2242C Datasheet, PDF (2/16 Pages) Fairchild Semiconductor – Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz

PRODUCT SPECIFICATION
TMC2242C
Functional Description
The TMC2242C implements a fixed-coefficient linear-phase
Finite Impulse Response (FIR) filter, with special rate-
matching input and output structures for decimation and
interpolation. For parts of each speed grade, the faster of
either the input or the output bus will operate at the respec-
tive guaranteed maximum clock rate. The total internal
pipeline latency from the input of an impulse to the corre-
sponding output peak (digital group delay) is 34 clock
cycles; the 39-value output response begins after 15 clock
cycles and ends after 53 cycles. (The double-latency interpo-
lation and decimation modes feature group delays of 68
clock cycles.)
To interpolate, the chip accepts incoming data on alternate
clock cycles, inserting zeroes on the remaining clock cycles.
In decimation mode, the chip’s output register is strobed at
half the clock rate. In bypass and equal-rate filter modes,
these input zero insertion and output register hold functions
are disabled.
When interpolating, the user should normally bring SYNC
HIGH for at least one clock cycle, returning it LOW with the
first desired input data value. The chip will then continue to
accept data on alternate rising edges of CLK. The user may
leave SYNC LOW or change its value once per clock cycle,
with equivalent results. The chip can be powered up and
operated with SYNC grounded, but the input-to-output
latency may vary by 1/2 input sample period and the host
system won’t know which (even- or odd-numbered) CLK
rising edges strobe the input register. The setup and hold tim-
ing requirements for SYNC, with respect to the rising edges
of CLK, are the same as those for all other data and control
inputs except OE, which is asynchronous. In two-channel
mode, it must remain low after the first incoming data value.
When decimating, the user should likewise bring SYNC
HIGH for at least one clock cycle, returning it LOW when a
fresh output is desired. The chip will continue to update the
output register on alternate rising edges of CLK. The user
may leave SYNC LOW or change its value once per clock
cycle, with equivalent results. The chip can be powered up
and operated with SYNC grounded, but the host system
won’t know whether the data outputs are updated on even- or
odd-numbered system clock cycles. In any half-band deci-
mating filter, a given single-cycle impulse’s arrival time (on
an odd versus an even clock cycle) determines whether it
generates a half-amplitude two-cycle impulse or a half-
speed, 40-clock, filtered output shaped by the nonzero, non-
center coefficients. The SYNC control permits the host sys-
tem to obtain consistent results. In two-channel mode, it
must remain low after the first incoming data value.
When the result is rounded to fewer than 16 bits, the
unneeded lowest positions of the output bus are tristated
and become supplementary control bits, which enable the
x/sin(x) filter, bypass/delay, double-latency, dual-channel,
and other special modes. Unless more than 12 output bits are
enabled, the TMC2242C offers x/sin(x) correction filtering,
with or without the main low-pass filter, and without impact-
ing the 34-cycle group delay. Bidirectional pins SO3-2
enable these modes, per Table 1. If 14 or more output bits are
used, the low pass filter remains enabled, the x/sin(x),
disabled.
Table 1. Operating Modes
INT DEC RND2 SO3-2
0
0
0 Output
0
1
0 Output
Function
Interpolate (0 dB)
Interpolate¹ (-6 dB)
1
0
0 Output
Decimate
1
1
0 Output Equal Rate Lowpass
0
0
1
00
Interpolate (0 dB)
0
11
00
Interpolate¹ (-6 dB)
1
0
1
00
Decimate
1
1
1
00 Equal Rate Lowpass
0
0
1
01
Interpolate (0 dB)
* x/sinx
0
11
01
Interpolate¹ (-6 dB)
* x/sinx
1
0
1
01
Decimate * x/sinx
1
1
1
01 Equal Rate LPF * x/sinx
0
0
1
10
Delay + Interpolate²
(0 dB)
0
1
1
10
Delay + Interpolate²
(0 dB) * x/sinx
1
0
1
10
Delay + Decimate²
1
1
1
10
Bypass (Delay Only)
0
0
1
11 2-Channel Interpolate³
(0 db)
0
1
1
11 2-Channel Interpolate³
* x/sinx
1
0
1
11 2-Channel Decimate³
1
1
1
11
Delay * x/sinx
Note:
1. These modes limit to 15 bits (SO14-0) instead of 16
(SO15-0) and are provided for backward compatibility to
earlier parts.
2. These modes, which double the chip’s overall group delay
from 34 to 68 CLK cycles, can be used to equalize inter-
component delays where Y is sampled at twice the rate of
CB or CR (e.g. 4:2:2 and 8:4:4 formats).
3. These modes accommodate multiplexed two-channel da-
ta, e.g. CB/CR.
2