FHP3392 Datasheet, PDF (2/7 Pages) Fairchild Semiconductor – Fixed-Gain, ±5V, Triple 2:1, High-Speed Video Multiplexer

Block Diagram and Pin Configuration
Figure 1. Block Diagram and Pin Configuration
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
IN1A
DGND
IN2A
GND
1N3A
+Vs
-Vs
IN3B
GND
IN2B
GND
IN1B
+VS
+DVs
-VS
OUT3
+Vs
OUT3
-VS
OUT1
+VS
SEL A/B
EN
+VS
Description
1st Input Channel A
Digital Ground, must be connected to ground
2nd Input Channel A
Must be connected to ground
3rd Input Channel A
Positive supply
Negative supply
3rd Input Channel B
Must be connected to ground
2nd Input Channel B
Must be connected to ground
1st Input Channel B
Positive supply
Digital positive supply
Negative supply
3rd output
Positive supply
2nd output
Negative supply
1st Output
Logic input; “0” = Channel A, “1” = Channel B
Enable pin; “0” = Enable, “1” = Disable; Enabled if left floating or grounded
Enable Pin: “0” = Channel A, “1” = Channel B
Positive supply
Truth Table
SEL A / B
0
1
X
EN
OUT
0
Channel A
0
Channel B
1
Disable
© 2006 Fairchild Semiconductor Corporation
FHP3392 Rev. 1.0.0
2
www.fairchildsemi.com