FDS89161 Datasheet, PDF (2/6 Pages) Fairchild Semiconductor – Dual N-Channel PowerTrench® MOSFET 100 V, 2.7 A, 105 mΩ

Electrical Characteristics T_J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BV_DSS
ΔBV_DSS
ΔT_J
I_DSS
I_GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I_D = 250 μA, V_GS = 0 V
I_D = 250 μA, referenced to 25 °C
V_DS = 80 V, V_GS = 0 V
V_GS = ±20 V, V_DS = 0 V
100
V
67
mV/°C
1
μA
±100 nA
On Characteristics
V_GS(th)
ΔV_GS(th)
ΔT_J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
r_DS(on)
Static Drain to Source On Resistance
g_FS
Forward Transconductance
V_GS = V_DS, I_D = 250 μA
2
I_D = 250 μA, referenced to 25 °C
V_GS = 10 V, I_D = 2.7 A
V_GS = 6 V, I_D = 2.1 A
V_GS = 10 V, I_D = 2.7 A, T_J = 125 °C
V_DS = 10 V, I_D = 2.7 A
3
4
V
-9
mV/°C
86
105
120
171
mΩ
144 176
5
S
Dynamic Characteristics
C_iss
C_oss
C_rss
R_g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V_DS = 50 V, V_GS = 0 V,
f = 1MHz
158 210
pF
43
58
pF
3
5
pF
1
Ω
Switching Characteristics
t_d(on)
t_r
t_d(off)
t_f
Q_g(TOT)
Q_g(TOT)
Q_gs
Q_gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V_DD = 50 V, I_D = 2.7 A,
V_GS = 10 V, R_GEN = 6 Ω
V_GS = 0 V to 10 V
V_GS = 0 V to 5 V
V_DD = 50 V,
I_D = 2.7 A
4.2
10
ns
1.3
10
ns
7.3
15
ns
1.9
10
ns
3
4.1
nC
1.7
2.4
0.8
nC
0.8
nC
Drain-Source Diode Characteristics
V_SD
Source to Drain Diode Forward Voltage
t_rr
Reverse Recovery Time
Q_rr
Reverse Recovery Charge
V_GS = 0 V, I_S = 2.7 A
V_GS = 0 V, I_S = 2 A
(Note 2)
(Note 2)
I_F = 2.7 A, di/dt = 100 A/μs
0.85 1.3
V
0.82 1.2
34
54
ns
21
34
nC
NOTES:
1. R_θJA is determined with the device mounted on a 1 in² pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R_θJC is guaranteed by design while R_θCA is determined by
the user's board design.
a) 78°C/W when
mounted on a 1 in²
pad of 2 oz copper
b) 135°C/W when
mounted on a
minimun pad
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting T_J = 25°C, L = 3 mH, I_AS = 3 A, V_DD = 100 V, V_GS = 10 V.
©2011 Fairchild Semiconductor Corporation
2
FDS89161 Rev. C2
www.fairchildsemi.com