FDS8840NZ Datasheet, PDF (2/6 Pages) Fairchild Semiconductor – N-Channel PowerTrench® MOSFET 40 V, 18.6 A, 4.5 mΩ

Electrical Characteristics T_J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BV_DSS
∆BV_DSS
∆T_J
I_DSS
I_GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I_D = 250 µA, V_GS = 0 V
I_D = 250 µA, referenced to 25 °C
V_DS = 32 V, V_GS = 0 V
V_GS = ±20 V, V_DS = 0 V
40
V
31
mV/°C
1
µA
±10
µA
On Characteristics
V_GS(th)
Gate to Source Threshold Voltage
V_GS = V_DS, I_D = 250 µA
1.0
1.8
3.0
V
∆V_GS(th)
∆T_J
Gate to Source Threshold Voltage
Temperature Coefficient
I_D = 250 µA, referenced to 25 °C
-6
mV/°C
V_GS = 10 V, I_D = 18.6 A
3.9
4.5
r_DS(on)
Static Drain to Source On Resistance
V_GS = 4.5 V, I_D = 14.9 A
4.6
6.0
mΩ
V_GS = 10 V, I_D = 18.6 A, T_J =125 °C
5.9
7.0
g_FS
Forward Transconductance
V_DS = 5 V, I_D = 18.6 A
83
S
Dynamic Characteristics
C_iss
C_oss
C_rss
R_g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V_DS = 20 V, V_GS = 0 V,
f = 1 MHz
5665 7535
pF
650
865
pF
445
670
pF
1.2
Ω
Switching Characteristics
t_d(on)
t_r
t_d(off)
t_f
Q_g
Q_g
Q_gs
Q_gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V_DD = 20 V, I_D = 18.6 A,
V_GS = 10 V, R_GEN = 6 Ω
V_GS = 0 V to 10 V
V_GS = 0 V to 5 V
V_DD = 20 V,
I_D = 18.6 A
18
32
ns
13
23
ns
57
103
ns
11
20
ns
103
144
nC
54
76
nC
16
nC
19
nC
Drain-Source Diode Characteristics
V_SD
Source to Drain Diode Forward Voltage ^{VGS = 0 V, IS = 18.6 A}
V_GS = 0 V, I_S = 2.1 A
0.8
1.2
V
0.7
1.2
t_rr
Reverse Recovery Time
Q_rr
Reverse Recovery Charge
I_F = 18.6 A, di/dt = 100 A/µs
33
53
ns
21
34
nC
NOTES:
1. R_θJA is determined with the device mounted on a 1 in² pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R_θJC is guaranteed by design while R_θCA is determined by
the user's board design.
a) 50 °C/W when mounted on a
1 in² pad of 2 oz copper.
b) 125 °C/W when mounted on a
minimum pad.
2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%.
3. The diode connected between the gate and source servers only as protection against ESD. No gate overvoltage rating is implied.
4. Starting T_J = 25 °C, L = 3 mH, I_AS = 20 A, V_DD = 40 V, V_GS = 10 V.
©2009 Fairchild Semiconductor Corporation
2
FDS8840NZ Rev.C1
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