FDD86102LZ_12 Datasheet, PDF (2/6 Pages) Fairchild Semiconductor – N-Channel PowerTrench® MOSFET 100 V, 35 A, 22.5 mΩ

Electrical Characteristics T_J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BV_DSS
ΔBV_DSS
ΔT_J
I_DSS
I_GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I_D = 250 μA, V_GS = 0 V
100
V
I_D = 250 μA, referenced to 25 °C
69
mV/°C
V_DS = 80 V, V_GS = 0 V
V_GS = ±20 V, V_DS = 0 V
1
μA
±10
μA
On Characteristics (Note 2)
V_GS(th)
ΔV_GS(th)
ΔT_J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
r_DS(on)
Static Drain to Source On Resistance
g_FS
Forward Transconductance
V_GS = V_DS, I_D = 250 μA
1.0
I_D = 250 μA, referenced to 25 °C
V_GS = 10 V, I_D = 8 A
V_GS = 4.5 V, I_D = 7 A
V_GS = 10 V, I_D = 8 A, T_J = 125 °C
V_DS = 5 V, I_D = 8 A
1.5
3.0
V
-6
mV/°C
17.8 22.5
23.2
31
mΩ
31.1
40
31
S
Dynamic Characteristics
C_iss
C_oss
C_rss
R_g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V_DS = 50 V, V_GS = 0 V,
f = 1 MHz
1157 1540 pF
181
245
pF
7.7
15
pF
0.6
Ω
Switching Characteristics
t_d(on)
t_r
t_d(off)
t_f
Q_g
Q_g
Q_gs
Q_gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V_DD = 50 V, I_D = 8 A,
V_GS = 10 V, R_GEN = 6 Ω
V_GS = 0 V to 10 V
V_GS = 0 V to 4.5 V V_DD = 50 V,
I_D = 8 A
6.6
14
ns
2.3
10
ns
20
32
ns
2.3
10
ns
18
26
nC
8.7
13
nC
2.7
nC
2.4
nC
Drain-Source Diode Characteristics
V_SD
Source to Drain Diode Forward Voltage
V_GS = 0 V, I_S = 8 A
V_GS = 0 V, I_S = 2.6 A
(Note 2)
(Note 2)
0.82
1.3
V
0.75
1.2
t_rr
Reverse Recovery Time
Q_rr
Reverse Recovery Charge
I_F = 8 A, di/dt = 100 A/μs
43
70
ns
43
70
nC
Notes:
1. R_θJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R_θJC is guaranteed by design while R_θJA is determined by the user’s board design.
a. 40 °C/W when mounted on a
1 in² pad of 2 oz copper.
b. 96 °C/W when mounted on a
minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting T_J = 25°C, L = 1 mH, I_AS = 13 A, V_DD = 90 V, V_GS = 10 V.
4. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
©2012 Fairchild Semiconductor Corporation
2
FDD86102LZ Rev.C1
www.fairchildsemi.com