FAN6753 Datasheet, PDF (2/12 Pages) Fairchild Semiconductor – Highly Integrated Green-Mode PWM Controller

Marking Information
ZXYTT
6753
TPM
F: Fairchild Logo
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M:SOP)
P: Y=Green Package
M: Manufacture Flow Code
Figure 1. Top Mark
Pin Configuration
SOP-8
LATCH 1
FB 2
SENSE 3
GND 4
8 HV
7 NC
6
VDD
5 GATE
Figure 2. Pin Configuration (Top View)
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
Name
LATCH
FB
SENSE
GND
GATE
VDD
NC
HV
Description
For external latch circuit used. When VLATCHth > 5.2V and after 100µs, IC is latched off.
10KΩ to GND is recommended. Internal has a sourcing current of 100µA (ILATCH), 100µA
×10KΩ. The voltage on this pin is 1V (under VLATCHth=5.2V).
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal on this pin and the current-sense signal on the SENSE pin.
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
Ground.
The totem-pole output driver. Soft-driving waveform is implemented for improved EMI.
Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
No connection.
For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
2
www.fairchildsemi.com