FAN4810EVAL Datasheet, PDF (2/6 Pages) Fairchild Semiconductor – Power Factor Controller

FAN4810EVAL
PRODUCT SPECIFICATION
FAN4810 with 500 Watt Load
97
7.5
96
95
94
93
92
91
90
89
90
7
6.5
6
5.5
5
Efficiency 4.5
THD
4
110 130 150 170 190 210 230 250
V line (RMS)
Figure 1. FAN4810 Evaluation Board Test Results
Test Conditions: 500 Watt load on output at 25ºC
Equipment Used: Voltech Digital Single-Phase Power
Analyzer Model PM100, 500W Electronic load.
Power Ratings
500
480
Pout
460
440
420
400
85 90 95 100 105 110 115
Input (VAC)
Figure 2. Output Power vs. Line Voltage
The FAN4810 Evaluation Board is designed to provide up to
500W output with an input of 90VAC. Due to thermal limita-
tions the actual output with no fan is limited to ≤400W at
inputs below 115VAC, and up to 40ºC ambient. Figure 2
displays the maximum power vs. line voltage with no fan.
Above 115VAC input the maximum output power is 500W.
The unit will safely provide 500W at 90 VAC input with
adequate fan cooling. Note that even though the FAN4810
Evaluation board can achieve 500 Watts with additional fan
cooling, the heatsinks utilized are not optimal for use with
a fan.
Layout Considerations
The FAN4810 Evaluation board contains high impedance,
low-level signals and low impedance, high level circuits;
consequently extra care is required in component placement,
grounding and PC trace routing. In order to shield low-level
circuits from the high level signals, control circuits were
placed in surface mount form on the bottom side of the
board. This allowed a return shield to be placed on the top-
side. Since the current sense for the FAN4810 is not differen-
tial, care must be taken to prevent a large di/dt from occur-
ring across the PCB trace joining the output cap (assumed to
be the reference return for the IC) to the current sense resis-
tor. Since the best reference for the IC is at the output cap
return potential (the most stable potential), the difference
between this potential and the current sense resistor return
potential must be kept to a minimum. This is done by star-
grounding all the 400V return connections to the output
capacitor, and/or maintaining very low inductive/resistive
paths from all power devices to the output capacitor return.
Some general layout guidelines:
A. Return the low side of the timing capacitor (C18)
directly to the IC ground pin.
B. Bypass the reference and supply voltage pins directly to
the IC ground pin with a 1 µF, low ESR/ESL capacitor.
C. Return all compensation components directly to the IC
ground pin, keeping the lead lengths as short as possible.
D. Make sure that low-level, noise free, returns do not share
return paths with high-level, or noisy, signals (e.g., gate
drive).
E. Isolate and/or shield rapidly changing waveforms, such
as the drain of Q1 from sensitive, high impedance cir-
cuits, such as the timing capacitor, PFC current sense
input, error amplifier input/output, etc.
2
REV. 1.0.2 6/17/04