DM74AS646 Datasheet, PDF (2/8 Pages) Fairchild Semiconductor – Octal Bus Transceiver and Register

Connection Diagram
Function Table
Inputs
Data I/O (Note 1)
Operation or Function
G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8
DM74AS646
H X H or L H or L X X
Input
Input Isolation, Hold Storage
X
↑
↑
XX
Store A and B Data
DM74AS648
Isolation, Hold Storage
Store A and B Data
LL
L
X
X XL
X H or L X H
Output
Input
Real Time B Data to A Bus Real Time B Data to A Bus
Stored B Data to A Bus Stored B Data to A Bus
LH X
X
LX
Input
Output Real Time A Data to B Bus Real Time A Data to B Bus
H H or L X H X
Stored A Data to B Bus Stored A Data to B Bus
X
X
↑
X XX
Input Unspecified Store A, B Unspecified
Store A, B Unspecified
(Note 1)
(Note 1)
(Note 1)
X
XX
↑
X X Unspecified Input Store B, A Unspecified
Store B, A Unspecified
(Note 1)
(Note 1)
(Note 1)
H—HIGH level; L—LOW level; X—irrelevant; ↑—LOW-to-HIGH level transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
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