74LVTH16835 Datasheet, PDF (2/7 Pages) Fairchild Semiconductor – Low Voltage 18-Bit Universal Bus Driver with 3-STATE Outputs (Preliminary)

Connection Diagram
Preliminary
Pin Descriptions
Pin Names
Description
A₁–A₁₈
Y₁–Y₁₈
CLK
Data Register Inputs
3-STATE Outputs
Clock Pulse Input
OE
Output Enable Input
LE
Latch Enable Input
Truth Table
Inputs
OE LE CLK A
Output
Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
H
X Y₀ (Note 1)
L
L
L
X Y₀ (Note 2)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
↑ = HIGH-to-LOW Clock Transition
Note 1: Output level before the indicated steady-state input conditions
were established, provided that CLK was HIGH before LE went LOW.
Note 2: Output level before the indicated steady-state input conditions
were established.
Logic Diagram
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