74LVT16646 Datasheet, PDF (2/9 Pages) Fairchild Semiconductor – Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs

Connection Diagram
Pin Descriptions
Pin Names
Description
A₀–A₁₅
Data Register A Inputs/3-STATE Outputs
B₀–B₁₅
Data Register B Inputs/3-STATE Outputs
CPAB_n, CPBA_n Clock Pulse Inputs
SAB_n, SBA_n
Select Inputs
OE₁, OE₂
Output Enable Inputs
DIR_n
Direction Control Inputs
Truth Table
(Note 1)
OE₁
Inputs
DIR₁ CPAB₁ CPBA₁ SAB₁ SBA₁
Data I/O
A_0–7 B_0–7
Output Operation Mode
H
H
H
X
X
X
H or L
 _{ X}
H or L
X
X
X
X
X
Isolation
X Input Input Clock A_n Data into A Register
X
Clock B_n Data Into B Register
L
L
H
H
^X
X
X
L
L
X
A_n to B_n—Real Time (Transparent Mode)
X Input Output Clock A_n Data to A Register
L
L
H
H
^{H or L}
X
X
H
H
X
X
A Register to B_n (Stored Mode)
Clock A_n Data into A Register and Output to B_n
L
L
L
L
X
X
^X
X
X
L
B_n to A_n—Real Time (Transparent Mode)
L Output Input Clock B_n Data into B Register
L
L
L
L
X
X
^{H or L}
X
X
H
H
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
= LOW-to-HIGH Transition.
B Register to A_n (Stored Mode)
Clock B_n into B Register and Output to A_n
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control
pins.
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