74LCX374_07 Datasheet, PDF (2/14 Pages) Fairchild Semiconductor – Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Logic Symbol
D0 D1 D2 D3 D4 D5 D6 D7
CP
OE
O0 O1 O2 O3 O4 O5 O6 O7
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
OE 1
O0 2
D0 3
D1 4
O1 5
O2 ₆
D2 7
D3 8
O3 9
GND 10
20 V_CC
19 O7
18 D7
17 D₆
16 O6
15 ^O5
14 D5
13 D4
12 O4
11 CP
Pad Assignments for DQFN
OE VCC
1 20
O0 2
D0 3
D1 4
O1 5
O2 6
D2 7
D3 8
O3 9
19 O₇
18 D₇
17 D₆
16 O₆
15 O₅
14 D₅
13 D₄
12 O₄
10 11
GND CP
(Top View)
Pin Descriptions
Pin Names
D₀–D₇
CP
OE
O₀–O₇
Description
Data Inputs
Clock Pulse Input
Output Enable Input
3-STATE Outputs
Truth Table
Inputs
Outputs
D_n
CP
OE
O_n
H
L
H
L
L
L
X
L
L
O₀
X
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
O₀ = Previous O₀ before HIGH-to-LOW of CP
Functional Description
The LCX374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) tran-
sition. With the Output Enable (OE) LOW, the contents of
the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Logic Diagram
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
CP
CP D
O
CP D
O
CP D
O
CP D
O
CP D
O
CP D
O
CP D
O
CP D
O
OE
O₀
O₁
O₂
O₃
O₄
O₅
O₆
O₇
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
74LCX374 Rev. 2.0.0
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