74LCX32374 Datasheet, PDF (2/8 Pages) Fairchild Semiconductor – Low Voltage 32-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Preliminary

Preliminary
Connection Diagram
Pin Descriptions
(Top Thru View)
Functional Description
The LCX32374 consists of thirty-two edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte func-
tioning identically, but independent of the other. The control
pins can be shorted together to obtain full 32-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP_n)
transition. With the Output Enable (OE_n) LOW, the con-
tents of the flip-flops are available at the outputs. When
OE_n is HIGH, the outputs go to the high impedance state.
Operation of the OE_n input does not affect the state of the
flip-flops.
Pin Names
Description
OE_n
CP_n
I₀–I₃₁
O₀–O₃₁
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
FBGA Pin Assignments
1
2
3
4
5
6
A
O₁
O₀ OE₁ CP₁
I₀
I₁
B
O₃
O₂ GND GND I₂
I₃
C
O₅
O₄
V_CC V_CC
I₄
I₅
D
O₇
O₆ GND GND I₆
I₇
E
O₉
O₈ GND GND I₈
I₉
F
O₁₁
O₁₀ V_CC V_CC
I₁₀
I₁₁
G
O₁₃ O₁₂ GND GND I₁₂
I₁₃
H
O₁₄ O₁₅ OE₂ CP₂ I₁₅
I₁₄
J
O₁₇ O₁₆ OE₃ CP₃ I₁₆
I₁₇
K
O₁₉ O₁₈ GND GND I₁₈
I₁₉
L
O₂₁ O₂₀ V_CC V_CC
I₂₀
I₂₁
M
O₂₃ O₂₂ GND GND I₂₂
I₂₃
N
O₂₅ O₂₄ GND GND I₂₄
I₂₅
P
O₂₇ O₂₆ V_CC V_CC
I₂₆
I₂₇
R
O₂₉ O₂₈ GND GND I₂₈
I₂₉
T
O₃₀ O₃₁ OE₄ CP₄ I₃₁
I₃₀
Truth Table
Inputs
^CPn
OE_n
L
L
I_n
H
L
L
L
X
X
H
X
X = Immaterial
Z = High Impedance
O₀ = Previous O₀ before HIGH-to-LOW of CP
Outputs
O_n
H
L
O₀
Z
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