74LCX112 Datasheet, PDF (2/9 Pages) Fairchild Semiconductor – Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs

Truth Table
(Each half)
Inputs
Outputs
S_D
C_D
CP
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
H

h
H

l
h
Q_O
Q_O
h
L
H
H
H
h
l
H
L
H
H
l
l
Q_O
Q_O
H
H
H
X
X
Q_O
Q_O
H(h) = HIGH Voltage Level
L(l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q_O(Q_O) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
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