74F845 Datasheet, PDF (2/6 Pages) Fairchild Semiconductor – 8-Bit Transparent Latch

Unit Loading/Fan Out
Pin Names
D₀–D₇
O₀–O₇
OE₁–OE₃
LE
CLR
PRE
Description
Data Inputs
Data Outputs
Output Enables
Latch Enable
Clear
Preset
U.L.
HIGH/LOW
1.0/1.0
150/40
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
−3.0 µA/24 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
Functional Description
The 74F845 consists of eight D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation as the output transition follows the data in transi-
tion. On the LE HIGH-to-LOW transition, the data that
meets the setup times is latched. Data appears on the bus
when the output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
Function Table
Inputs
CLR PRE OE LE
HHHX
H H HH
H H HH
HHHL
HH LH
HH LH
HH L L
HL LX
LHLX
L L LX
L HHL
H L HL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Internal Output
Function
D
Q
O
X
X
Z High Z
L
L
Z High Z
H
H
Z High Z
X NC
Z Latched
L
L
L Transparent
H
H
H Transparent
X NC
NC Latched
X
H
H Preset
X
L
L Clear
X
H
H Preset
X
L
Z Latched
X
H
Z Latched
Z = High Impedance
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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