74F841 Datasheet, PDF (2/6 Pages) NXP Semiconductors – Bus interface latches

Unit Loading/Fan Out
Pin Names
D₀–D₉
O₀–O₉
OE
LE
Description
Data Inputs
3-STATE Outputs
Output Enable Input
Latch Enable
U.L.
HIGH/LOW
1.0/1.0
150/40
1.0/1.0
1.0/1.0
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
−3 mA/24 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
Functional Description
The 74F841 device consists of ten D-type latches with 3-
STATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asyn-
chronous operation, as the output transition follows the
data in transition.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH
the bus output is in the high impedance state.
Function Table
Inputs
Internal Output
OE LE D
Q
O
XXX
X
Z
HH L
L
Z
HHH
H
Z
H L X NC
Z
LHL
L
L
L HH
H
H
L L X NC
NC
LXX
H
H
LXX
L
L
LXX
H
H
HLX
L
Z
HLX
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
NC = No Change
Function
High Z
High Z
High Z
Latched
Transparent
Transparent
Latched
Preset
Clear
Preset
Latched
Latched
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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