74F823 Datasheet, PDF (2/6 Pages) Fairchild Semiconductor – 9-Bit D-Type Flip-Flop

Unit Loading/Fan Out
Pin Names
D₀–D₈
OE
CLR
CP
EN
O₀–O₈
Description
Data Inputs
Output Enable Input
Clear
Clock Input
Clock Enable
3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
150/40 (33.3)
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Functional Description
The 74F823 device consists of nine D-type edge-triggered
flip-flops. It has 3-STATE true outputs and is organized in
broadside pinning. The buffered Clock (CP) and buffered
Output Enable (OE) are common to all flip-flops. The flip-
flops will store the state of their individual D inputs that
meet the setup and hold times requirements on the LOW-
to-HIGH CP transition. With the OE LOW the contents of
the flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops. In addition to the Clock and Output Enable pins, the
74F823 has Clear (CLR) and Clock Enable (EN) pins.
When the CLR is LOW and the OE is LOW, the outputs are
LOW. When CLR is HIGH, data can be entered into the flip-
flops. When EN is LOW, data on the inputs is transferred to
the outputs on the LOW-to-HIGH clock transition. When
the EN is HIGH, the outputs do not change state regard-
less of the data or clock inputs transitions. This device is
ideal for parity bus interfacing in high performance sys-
tems.
Function Table
Inputs
Internal Output
OE CLR EN CP D Q
O
Function
H H L H X NC
Z Hold
H H L L X NC
Z Hold
H H H X X NC
Z Hold
L H H X X NC
NC Hold
H L X XX H
Z Clear
L
H
H
L
L
L
H
H
H
H
X XX
 L
H
 L
H
 L
L
 L
H
H
H
L
H
L
L Clear
Z Load
Z Load
L Data Available
H Data Available
L H L H X NC
NC No Change in Data
L H L L X NC
NC No Change in Data
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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