74F821 Datasheet, PDF (2/6 Pages) NXP Semiconductors – Bus interface registers

Unit Loading/Fan Out
Pin Names
D₀–D₉
OE
CP
O₀–O₉
Description
Data Inputs
Output Enable
3-STATE Input
Clock Input
3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
1.0/1.0
20 µA/−0.6 mA
150/40 (33.3) −3.0 mA/24 mA (20 mA)
Functional Description
The 74F821 consists of ten D-type edge-triggered flip-
flops. This device has 3-STATE true outputs for bus sys-
tems organized in a broadside pinning. The buffered Clock
(CP) and buffered Output Enable (OE) are common to all
flip-flops. The flip-flops will store the state of their individual
D inputs that meet the setup and hold times requirements
on the LOW-to-HIGH CP transition. With the OE LOW the
content of the flip-flops are available at the outputs. When
the OE is HIGH, the outputs go to the high impedance
state. Operation of the OE input does not affect the state of
the flip-flops.
Function Table
Inputs
OE CP D
HHX
H
H
H
L
L
^L
X
L
H
L
H
LHX
LLX
Internal Output
Q
O
Function
NC
Z Hold
NC
Z Hold
H
Z Load
L
Z Load
H
L Data Available
L
H Data Available
NC
NC No Change in Data
NC
NC No Change in Data
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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