74F74 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Dual D-type flip-flop

Unit Loading/Fan Out
Pin Names
Description
D₁, D₂
CP₁, CP₂
C_D1, C_D2
S_D1, S_D2
Q₁, Q₁, Q₂, Q₂
Truth Table
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
50/33.3
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.8 mA
20 µA/−1.8 mA
−1 mA/20 mA
Inputs
Outputs
S_D
C_D
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H

h
H
L
H
H

l
L
H
H
H
L
X
Q₀
Q₀
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
Q₀ = Previous Q (Q) before LOW-to-HIGH Clock Transition
Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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