74F675A Datasheet, PDF (2/6 Pages) Fairchild Semiconductor – 16-Bit Serial-In, Serial/Parallel-Out Shift Register

Unit Loading/Fan Out
Pin Names
SI
CS
SHCP
STCP
R/W
SO
Q₀–Q₁₅
Description
Serial Data Input
Chip Select Input (Active LOW)
Shift Clock Pulse Input (Active Falling Edge)
Store Clock Pulse Input (Active Rising Edge)
Read/Write Input
Serial Data Output
Parallel Data Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
The 16-Bit shift register operates in one of four modes, as
determined by the signals applied to the Chip Select (CS),
Read/Write (R/W) and Store Clock Pulse (STCP) input.
State changes are indicated by the falling edge of the Shift
Clock Pulse (SHCP). In the Shift Right mode, data enters
D₀ from the Serial Input (SI) pin and exits from Q₁₅ via the
Serial Data Output (SO) pin. In the Parallel Load mode,
data from the storage register outputs enter the shift regis-
ter and serial shifting is inhibited.
The storage register is in the Hold mode when either CS or
R/W is HIGH. With CS and R/W both LOW, the storage
register is parallel loaded from the shift register on the ris-
ing edge of STCP.
To prevent false clocking of the shift register, SHCP should
be in the LOW state during a LOW-to-HIGH transition of
CS. To prevent false clocking of the storage register, STCP
should be LOW during a HIGH-to-LOW transition of CS if
R/W is LOW, and should also be LOW during a HIGH-to-
LOW transition of R/W if CS is LOW.
Shift Register Operations Table
Control Inputs
Operating
CS R/W SHCP STCP
Mode
H
L
L
L
X
L
H
H
^X
X Hold
X Shift Right
L Shift Right
H Parallel Load,
No Shifting
Logic Diagram
Storage Register Operations Table
Inputs
CS
R/W
H
X
L
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
 = HIGH-to-LOW Transition
 = LOW-to-HIGH Transition
Operating
STCP
X
^X
Mode
Hold
Hold
Parallel Load
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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