74F673A Datasheet, PDF (2/7 Pages) Fairchild Semiconductor – 16-Bit Serial-In, Serial/Parallel-Out Shift Register

Unit Loading/Fan Out
Pin Names
CS
SHCP
STMR
STCP
R/W
SI/O
Q₀–Q₁₅
Description
Chip Select Input (Active LOW)
Shift Clock Pulse Input (Active Falling Edge)
Store Master Reset Input (Active LOW)
Store Clock Pulse Input
Read/Write Input
Serial Data Input or
3-STATE Serial Output
Parallel Data Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
3.5/1.0
150/40
50/33.3
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
70 µA/−0.6 mA
−3 mA/24 mA
−1 mA/20 mA
Functional Description
The 16-bit shift register operates in one of four modes, as
indicated in the Shift Register Operations Table. A HIGH
signal on the Chip Select (CS) input prevents clocking and
forces the Serial Input/Output (SI/O) 3-STATE buffer into
the high impedance state. During serial shift-out opera-
tions, the SI/O buffer is active (i.e., enabled) and the output
data is also recirculated back into the shift register. When
parallel loading the shift register from the storage register,
serial shifting is inhibited.
The storage register has an asynchronous master reset
(STMR) input that overrides all other inputs and forces the
Q₀–Q₁₅ outputs LOW. The storage register is in the Hold
mode when either CS or the Read/Write (R/W) input is
HIGH. With CS and R/W both LOW, the storage register is
parallel loaded from the shift register.
Shift Register Operations Table
Control Inputs
SI/O
CS R/W SHCP STCP Status
Operating Mode
HX X
X High Z Hold
LL
 L H
X Data In Serial Load
L Data Out Serial Output
 L H
H Active
with Recirculation
Parallel Load;
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Transition
No Shifting
Storage Register Operations Table
Control Inputs
Operating
STMR CS R/W STCP
Mode
L
X
X
X Reset; Outputs LOW
H
H
X
X Hold
H
X
H
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
X Hold
 Parallel Load
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