74F651 Datasheet, PDF (2/8 Pages) Fairchild Semiconductor – Transceivers/Registers

Logic Symbols
74F651
IEEE/IEC
74F651
74F652
IEEE/IEC
74F652
Unit Loading/Fan Out
Pin Names
A₀–A₇, B₀–B₇
CPAB, CPBA
SAB, SBA
OEAB, OEBA
Description
A and B Inputs/
3-STATE Outputs
Clock Inputs
Select Inputs
Output Enable Inputs
U.L.
HIGH/LOW
1.0/1.0
600/106.6 (80)
1.0/1.0
1.0/1.0
1.0/1.0
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
−12 mA/64 mA (48 mA)
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
Function Table
Inputs
Inputs/Outputs (Note 1)
OEAB OEBA CPAB CPBA SAB SBA A₀ thru A₇ B₀ thru B₇
Operating Mode
L
L
X
H
L
L
H
H
H
H
X
L
H or L H or L
 _{H or L}
  _{H or L}
X
X
X
X
X
X
X Input
Input
Isolation
X
Store A and B Data
X Input
Not Specified Store A, Hold B
X Input
Output
Store A in Both Registers
X Not Specified Input
Hold A, Store B
X Output
Input
Store B in Both Registers
L
L
X
X X L Output
Input
Real-Time B Data to A Bus
L
L
X H or L X H
Store B Data to A Bus
H
H
X
X L X Input
Output
Real-Time A Data to B Bus
H
H H or L X H X
Stored A Data to B Bus
H
L H or L H or L H H Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
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