74F646_04 Datasheet, PDF (2/6 Pages) Fairchild Semiconductor – Octal Transceiver/Register with 3-STATE Outputs

Unit Loading/Fan Out
Pin Names
A₀–A₇
B₀–B₇
CPAB, CPBA
SAB, SBA
G
DIR
Description
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
U.L.
HIGH/LOW
3.5/1.083
600/106.6 (80)
3.5/1.083
600/106.6 (80)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
Input I_IH/I_IL
Output I_OH/I_OL
70 µA/−650 µA
−12 mA/64 mA (48 mA)
70 µA/−650 µA
−12 mA/64 mA (48 mA)
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
Function Table
Inputs
Data I/O (Note 1)
G DIR CPAB CPBA SAB SBA A₀–A₇ B₀–B₇
Function
H
H
H
X
X
X
H or L H or L
X
 X
X
X
X
X
X Input
X
L
L
H
H
^X
X
X
L
L
X
X Input
L
L
 ^{H H or L X}
H
X
H
H
X
X
L
L
L
L
X
X
^X
X
X
L
L Output
L
L
L
L
 ^{X H or L X}
X
X
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
Isolation
Input Clock A_n Data into A Register
Clock B_n Data into B Register
A_n to B_n—Real Time (Transparent Mode)
Output Clock A_n Data into A Register
A Register to B_n (Stored Mode)
Clock A_n Data into A Register and Output to B_n
B_n to A_n—Real Time (Transparent Mode)
Input Clock B_n Data into B Register
B Register to A_n (Stored Mode)
 ^{Clock Bn Data into B Register and Output to An}
X = Irrelevant
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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