74F620 Datasheet, PDF (2/6 Pages) NXP Semiconductors – Octal bus transceiver, inverting 3tate

Unit Loading/Fan Out
Pin Names
Description
GBA, GAB
A₀–A₇
B₀–B₇
Enable Inputs
A Inputs or
3-STATE Outputs
B Inputs or
3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
3.5/1.083
150/40
3.5/1.083
150/40
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
70 µA/−0.4 mA
−3 mA/64 mA
70 µA/−0.4 mA
−3 mA/64 mA
Functional Description
The enable inputs GAB and GBA control whether data is
transmitted from the A bus to the B bus or from the B bus to
the A bus. If both GBA and GAB are disabled (GBA HIGH
and GAB LOW), the outputs are in the high impedance
state and data is stored at the A and B busses. When GBA
is active LOW, B data is sent to the A bus. When GAB is
active HIGH, data from the A bus is sent to the B bus. If
both enable inputs are active (GBA LOW and GAB HIGH)
B data is sent to the A bus while A data is sent to the B bus.
Logic Diagrams
Function Table
Enable Inputs
Operation
GBA GAB
74F620
74F623
L
L B Data to A Bus B Data to A Bus
H
H A Data to B Bus A Data to B Bus
H
L
Z
Z
L
H B Data to A Bus, B Data to A Bus,
A Data to B Bus A Data to B Bus
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
74F620
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F623
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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