74F579 Datasheet, PDF (2/7 Pages) NXP Semiconductors – 8-bit bidirectional binary counter 3-State

Unit Loading/Fan Out
Pin Names
I/O₀–I/O₇
PE
U/D
MR
SR
CEP
CET
CS
OE
CP
TC
Description
Data Inputs or
3-STATE Outputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Chip Select Input Active (Active LOW)
Output Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Terminal Count Output (Active LOW)
U.L.
HIGH/LOW
3.5/0.333
75/15
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
25/12.5
Input I_IH/I_IL
Output I_OH/I_OL
70 µA/−0.2 mA
−3 mA/24 mA
5 µA/−0.2 mA
5 µA/−0.2 mA
5 µA/−0.2 mA
5 µA/−0.2 mA
5 µA/−0.2 mA
5 µA/−0.2 mA
5 µA/−0.2 mA
5 µA/−0.2 mA
5 µA/−0.2 mA
−1 mA/5 mA
Function Table
MR SR CS PE CEP CET U/D OE CP
XXHXXXXXX
X X L HXXXHX
XX L HXXX L X
L
H
H
H
H
H
H
X
L
H
H
H
H
H
XX
XX
LL
(Not LL)
(Not LL)
(Not LL)
(Not LL)
X
X
X
H
X
L
L
X
X
X
X
H
L
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
^X

Function
I/O_a to I/O_h in High Z (PE Disabled)
I/O_a to I/O_h in High Z
Flip-Flop Outputs Appear on I/O Lines
Asynchronous Reset for all Flip-Flops
Synchronous Reset for all Flip-Flops
Parallel Load all Flip-Flops
Hold
Hold (TC Held HIGH)
Count Up
Count Down
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW to HIGH Clock Transition
Not LL = CS and PE should never both be LOW voltage level at the same time.
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