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74F573 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Octal transparent latch 3-State
Unit Loading/Fan Out
Pin Names
Description
D0–D7
LE
OE
O0–O7
Data Inputs
Latch Enable Input (Active HIGH)
3-STATE Output Enable Input (Active LOW)
3-STATE Latch Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40(33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Functional Description
The 74F573 contains eight D-type latches with 3-state out-
put buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-state buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Function Table
Inputs
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
O0 = Value stored from previous clock cycle
Outputs
O
H
L
O0
Z
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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