74F564 Datasheet, PDF (2/6 Pages) NXP Semiconductors – Octal D flip-flop 3-State

Unit Loading/Fan Out
Pin Names
D₀–D₇
CP
OE
O₀–O₇
Description
U.L.
HIGH/LOW
Input I_IH/I_IL
Output I_OH/I_OL
Data Inputs
1.0/1.0
20 µA/−0.6 mA
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 µA/−0.6 mA
3-STATE Output Enable Input (Active LOW) 1.0/1.0
20 µA/−0.6 mA
3-STATE Outputs
150/40 (33.3) −3 mA/24 mA (20 mA)
Functional Description
The 74F564 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Function Table
Inputs
Internal Outputs
OE CP D
Q
O
Function
H H L NC
Z Hold
H
H
H
L
L
^H
H
L
H
L
H
NC
H
L
H
L
Z Hold
Z Load
Z Load
H Data Available
L Data Available
L H L NC
NC No Change in Data
L H H NC
NC No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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