74F539 Datasheet, PDF (2/6 Pages) NXP Semiconductors – Dual 1-of-4 decoder 3-State

Unit Loading/Fan Out
Pin Names
Description
A_0a–A_1a
A_0b–A_1b
E_a, E_b
OE_a, OE_b
P_a, P_b
O_0a–O_3a
O_0b–O_3b
Side A Address Inputs
Side B Address Inputs
Enable Inputs (Active LOW)
Output Enable Inputs (Active LOW)
Polarity Control Inputs
Side A 3-STATE Outputs
Side B 3-STATE Outputs
Truth Table
(each half)
Function
OE
High Impedance
H
Disable
L
Active HIGH
L
Output
L
(P = L)
L
L
Active LOW
L
Output
L
(P = H)
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram (one half shown)
Inputs
E
A₁
X
X
H
X
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
H
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
150/40 (33.3)
A₀
O₀
X
Z
X
L
H
H
L
L
L
H
L
L
L
H
H
L
H
H
H
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
−3 mA/24 mA (20 mA)
Outputs
O₁
O₂
O₃
Z
Z
Z
O_n = P
L
L
L
H
L
L
L
H
L
L
L
H
H
H
H
L
H
H
H
L
H
H
H
L
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2