74F534 Datasheet, PDF (2/6 Pages) NXP Semiconductors – Latch/flip-flop

Unit Loading/Fan Out
Pin Names
Description
D₀–D₇
CP
OE
O₀–O₇
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-STATE Output Enable Input (Active LOW)
Complementary 3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40(33.3)
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Function Table
Inputs
CP
OE
D

L
H

L
L
L
L
X
X
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
^{X = Immaterial}
Z = High Impedance
= LOW-to-HIGH Clock Transition
O₀ = Value stored from previous clock cycle
Output
O
L
H
O₀
Z
Functional Description
The 74F534 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE complementary out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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