74F403A Datasheet, PDF (2/15 Pages) Fairchild Semiconductor – First-In First-Out (FIFO) Buffer Memory

Unit Loading/Fan Out:
See Section 2 for U.L. definitions
Pin
Names
Description
U.L.
Input I_IH/I_IL
HIGH/LOW Output IOH/IOL
D₀ − D₃ Parallel Data Inputs
D_S
Serial Data Input
PL
Parallel Load Input
CPSI Serial Input Clock
IES
Serial Input Enable
TTS Transfer to Stack Input
OES Serial Output Enable
TOS Transfer Out Serial
TOP Transfer Out Parallel
MR
Master Reset
OE
Output Enable
CPSO Serial Output Clock
Q₀ − Q₃ Parallel Data Outputs
Q_S
Serial Data Output
IRF
Input Register Full
ORE Output Register Empty
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
285/26.7
285/26.7
20/13.3
20/13.3
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
5.7 mA/16 mA
5.7 mA/16 mA
−400 µA/8 mA
−400 µA/8 mA
Block Diagram
Functional Description
As shown in the Block Diagram the 74F403A consists of
three sections:
1. An Input register with parallel and serial data inputs as
well as control inputs and outputs for input handshak-
ing and expansion.
2. A 4-bit wide, 14-word deep fall-through stack with self-
contained control logic.
3. An Output Register with parallel and serial data outputs
as well as control inputs and outputs for output hand-
shaking and expansion.
Since these three sections operate asynchronously and
almost independently, they will be described separately
below.
INPUT REGISTER (DATA ENTRY)
The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the
fall-through stack and generates the necessary status and
control signals.
Figure 1 is a conceptual logic diagram of the input section.
As described later, this 5-bit register is initialized by setting
the F₃ flip-flop and resetting the other flip-flops. The Q out-
put of the last flip-flop (FC) is brought out as the “Input
Register Full” output (IRF). After initialization this output is
HIGH.
Parallel Entry— A HIGH on the PL input loads the D₀-D₃
inputs into the F₀-F₃ flip-flops and sets the FC flip-flop. This
forces the IRF output LOW indicating that the input register
is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be
LOW to establish row mastership (see Expansion section).
Serial Entry— Data on the D_S input is serially entered into
the F₃, F₂, F₁, F₀, FC shift register on each HIGH-to-LOW
transition of the CPSI clock input, provided IES and PL are
LOW.
After the fourth clock transition, the four data bits are
located in the four flip-flops, F₀-F₃. The FC flip-flop is set,
forcing the IRF output LOW and internally inhibiting CPSI
clock pulses from affecting the register, Figure 2 illustrates
the final positions in a 74F403A resulting from a 64-bit
serial bit train. B₀ is the first bit, B₆₃ the last bit.
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