74F382 Datasheet, PDF (2/8 Pages) NXP Semiconductors – Arithmetic Logic Unit

Unit Loading/Fan Out
Pin Names
A₀–A₃
B₀–B₃
S₀–S₂
C_n
C_{n + 4}
OVR
F₀–F₃
Description
A Operand Inputs
B Operand Inputs
Function Select Inputs
Carry Input
Carry Output
Overflow Output
Function Outputs
U.L.
HIGH/LOW
1.0/4.0
1.0/4.0
1.0/1.0
1.0/5.0
50/33.3
50/33.3
50/33.3
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−2.4 mA
20 µA/−2.4 mA
20 µA/−0.6 mA
20 µA/−3.0 mA
−1 mA/20 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
Signals applied to the Select inputs S₀–S₂ determine the
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit performs the arith-
metic functions for either active HIGH or active LOW oper-
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the C_n input of the least significant package.
Ripple expansion is illustrated in Figure 2. The overflow
output OVR is the Exclusive-OR of C_{n + 3} and C_{n + 4}; a
HIGH signal on OVR indicates overflow in twos comple-
ment operation. Typical delays for Figure 2 are given in
Figure 1.
Function Select Table
Select
S₀
S₁
L
L
H
L
L
H
H
H
L
L
H
L
L
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
Operation
S₂
L Clear
L B Minus A
L A Minus B
L A Plus B
H A⊕B
H A+B
H AB
H Preset
Path Segment
Toward
F
A₁ or B₁ to C_{n + 4}
C_n to C_{n + 4}
C_n to C_{n + 4}
C_n to F
C_n to C_{n + 4}, OVR
Total Delay
6.5 ns
6.3 ns
6.3 ns
8.1 ns
—
27.2 ns
FIGURE 1. 16-Bit Delay Tabulation
Output
C_{n + 4}, OVR
6.5 ns
6.3 ns
6.3 ns
—
8.0 ns
27.1 ns
FIGURE 2. 16-Bit Ripply Carry ALU Expansion
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