74F381 Datasheet, PDF (2/8 Pages) NXP Semiconductors – Arithmetic Logic Unit

Unit Loading/Fan Out
Pin Names
A₀–A₃
B₀–B₃
S₀–S₂
C_n
G
P
F₀–F₃
Description
A Operand Inputs
B Operand Inputs
Function Select Inputs
Carry Input
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
Function Outputs
U.L.
HIGH/LOW
1.0/3.0
1.0/3.0
1.0/1.0
1.0/4.0
50/33.3
50/33.3
50/33.3
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−1.8 mA
20 µA/−1.8 mA
20 µA/−0.6 mA
20 µA/−2.4 mA
−1 mA/20 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
Signals applied to the Select inputs S₀–S₂ determine the
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit performs the arith-
metic functions for either active HIGH or active LOW oper-
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the C_n input of the least significant package.
The Carry Generate (G) and Carry Propagate (P) outputs
supply input signals to the 74F182 carry lookahead gener-
ator for expansion to longer word length, as shown in Fig-
ure 2. Note that an 74F382 ALU is used for the most
significant package. Typical delays for Figure 2 are given in
Figure 1.
Function Select Table
Select
S₀
S₁
S₂
Operation
L
L
L Clear
H
L
L B Minus A
L
H
L A Minus B
H
H
L A Plus B
L
L
H
L
L
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
H A⊕B
H A+B
H AB
H Preset
Path Segment
Toward
F
Output
C_n + 4, OVR
A_i or B_i to P
7.2 ns
7.2 ns
P_i to C_n + ('F182)
6.2 ns
6.2 ns
C_n to F
8.1 ns
—
C_n or C_n + 4, OVR
—
8.0 ns
Total Delay
21.5 ns
21.4 ns
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Lookahead Carry ALU Expansion
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