74F283_04 Datasheet, PDF (2/6 Pages) Fairchild Semiconductor – 4-Bit Binary Full Adder with Fast Carry

Functional Description
The 74F283 adds two 4-bit binary words (A plus B) plus the
incoming Carry (C₀). The binary sum appears on the Sum
(S₀–S₃) and outgoing carry (C₄) outputs. The binary weight
of the various inputs and outputs is indicated by the sub-
script numbers, representing powers of two.
2⁰ (A₀ + B₀ + C₀) + 2¹ (A₁ + B₁)
+ 2² (A₂ + B₂) + 2³ (A₃ + B₃)
= S₀ + 2S₁ + 4S₂ + 8S₃ + 16C₄
Where (+) = plus
Interchanging inputs of equal weight does not affect the
operation. Thus C₀, A₀, B₀ can be arbitrarily assigned to
pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier
packages. Due to the symmetry of the binary add function,
the 74F283 can be used either with all inputs and outputs
active HIGH (positive logic) or with all inputs and outputs
active LOW (negative logic). See Figure 1. Note that if C₀ is
not used it must be tied LOW for active HIGH logic or tied
HIGH for active LOW logic.
Due to pin limitations, the intermediate carries of the
74F283 are not brought out for use as inputs or outputs.
However, other means can be used to effectively insert a
carry into, or bring a carry out from, an intermediate stage.
Figure 2 shows how to make a 3-bit adder. Tying the oper-
and inputs of the fourth adder (A₃, B₃) LOW makes S₃
dependent only on, and equal to, the carry from the third
adder. Using somewhat the same principle, Figure 3 shows
a way of dividing the 74F283 into a 2-bit and a 1-bit adder.
The third stage adder (A₂, B₂, S₂) is used merely as a
means of getting a carry (C₁₀) signal into the fourth stage
(via A₂ and B₂) and bringing out the carry from the second
stage on S₂. Note that as long as A₂ and B₂ are the same,
whether HIGH or LOW, they do not influence S₂. Similarly,
when A₂ and B₂ are the same the carry into the third stage
does not influence the carry out of the third stage. Figure 4
shows a method of implementing a 5-input encoder, where
the inputs are equally weighted. The outputs S₀, S₁ and S₂
present a binary number equal to the number of inputs I₁–
I₅ that are true. Figure 5 shows one method of implement-
ing a 5-input majority gate. When three or more of the
inputs I₁–I₅ are true, the output M₅ is true.
C₀ A₀ A₁ A₂ A₃ B₀ B₁ B₂ B₃ S₀ S₁ S₂ S₃ C₄
Logic Levels
L LHLHHL LHHHL LH
Active HIGH
00101100111001
Active LOW
11010011000110
Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0
FIGURE 1. Active HIGH versus Active LOW Interpretation
FIGURE 2. 3-Bit Adder
FIGURE 3. 2-Bit and 1-Bit Adders
FIGURE 4. 5-Input Encoder
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FIGURE 5. 5-Input Majority Gate
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