74F194 Datasheet, PDF (2/7 Pages) NXP Semiconductors – 4-bit bidirectional universal shift register

Unit Loading/Fan Out
Pin Names
Description
S₀, S₁
P₀–P₃
D_SR
D_SL
CP
MR
Q₀–Q₃
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
Functional Description
The 74F194 contains four edge-triggered D-type flip-flops
and the necessary interstage logic to synchronously per-
form shift right, shift left, parallel load and hold operations.
Signals applied to the Select (S₀, S₁) inputs determine the
type of operation, as shown in the Mode Select Table. Sig-
nals on the Select, Parallel data (P₀–P₃) and Serial data
(D_SR, D_SL) inputs can change when the clock is in either
state, provided only that the recommended setup and hold
times, with respect to the clock rising edge, are observed.
A LOW signal on Master Reset (MR) overrides all other
inputs and forces the outputs LOW.
Mode Select Table
Operating
Inputs
Outputs
Mode
MR S₁ S₀ D_SR D_SL P_n Q₀ Q₁ Q₂ Q₃
Reset
L XX X X XLLLL
Hold
H l l X X X q₀ q₁ q₂ q₃
Shift Left
H h l X l X q₁ q₂ q₃ L
H h l X h X q₁ q₂ q₃ H
Shift Right H l h l X X L q₀ q₁ q₂
H l h h X X H q₀ q₁ q₂
Parallel Load H h h X X p_n p₀ p₁ p₂ p₃
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
p_n (q_n) = Lower case letters indicate the state of the referenced input (or
output) one setup time prior to the LOW-to-HIGH clock transition.
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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