74F113 Datasheet, PDF (2/6 Pages) NXP Semiconductors – Dual J-K negative edge-triggered flip-flops without reset

Unit Loading/Fan Out
Pin Names
Description
J₁, J₂, K₁, K₂
CP₁, CP₂
S_D1, S_D2
Q₁, Q₂, Q₁, Q₂
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Set Inputs (Active LOW)
Outputs
Truth Table
U.L.
HIGH/LOW
1.0/1.0
1.0/4.0
1.0/5.0
50/33.3
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−2.4 mA
20 µA/−3.0 mA
−1 mA/20 mA
Inputs
Outputs
S_D
CP
J
K
Q
Q
L
H
H
^X

X
h
l
X
h
h
H
Q₀
L
L
Q₀
H
H
h
l
H
L
H

l
l
Q₀
Q₀
H (h) = HIGH Voltage Level
^{L (l) = LOW Voltage level}
] = HIGH-to-LOW Clock Transition
X = Immaterial
Q₀ (Q₀) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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