74AUP1G97 Datasheet, PDF (2/11 Pages) NXP Semiconductors – Low-power configurable multiple function gate

Logic Diagram
3
A
1
B
6
C
Figure 1. Logic Diagram (Positive Logic)
Pin Configurations
B1
GND 2
A3
6C
5 VCC
4Y
Figure 2. MicroPak™ (Top Through View)
4Y
Pin Definitions
Pin #
1
2
3
4
5
6
Name
B
GND
A
Y
VCC
C
Description
Data Input
Ground
Data Input
Output
Supply Voltage
Data Input
© 2008 Fairchild Semiconductor Corporation
74AUP1G97 • 1.0.5
2
www.fairchildsemi.com