74AC74_05 Datasheet, PDF (2/10 Pages) Fairchild Semiconductor – Dual D-Type Positive Edge-Triggered Flip-Flop

Connection Diagram
Logic Symbols
Pin Descriptions
Pin Names
D₁, D₂
CP₁, CP₂
C_D1, C_D2
S_D1, S_D2
Q₁, Q₁, Q₂, Q₂
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
IEEE/IEC
Truth Table
(Each Half)
Inputs
Outputs
S_D C_D CP D
Q
Q
L
H
XXH
L
H
L
XXL
H
L
L
XXH
H
H
 H
HH
L
H
 H
L
L
H
H
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
LOW-to-HIGH Clock Transition
Q₀ (Q₀) Previous Q (Q) before LOW-to-HIGH Transition of Clock
L
X Q₀ Q₀
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