74AC169 Datasheet, PDF (2/8 Pages) Fairchild Semiconductor – 4-Stage Synchronous Bidirectional Counter

Functional Description
The AC169 uses edge-triggered J-K-type flip-flops and
have no constraints on changing the control or data input
signals in either state of the Clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over the other opera-
tions, as indicated in the Mode Select Table. When PE is
LOW, the data on the P₀–P₃ inputs enters the flip-flops on
the next rising edge of the Clock. In order for counting to
occur, both CEP and CET must be LOW and PE must be
HIGH; the U/D input then determines the direction of count-
ing. The Terminal Count (TC) output is normally HIGH and
goes LOW, provided that CET is LOW, when a counter
reaches zero in the Count Down mode or reaches 15 in the
Count Up mode. The TC output state is not a function of
the Count Enable Parallel (CEP) input level. If an illegal
state occurs, the AC169 will return to the legitimate
sequence within two counts. Since the TC signal is derived
by decoding the flip-flop states, there exists the possibility
of decoding spikes on TC. For this reason the use of TC as
a clock signal is not recommended (see logic equations
below).
1. Count Enable = CEP •CET • PE
2. Up: TC = Q₀•Q₁•Q ₂Q₃•(Up)•CET
3. Down: TC = Q₀• Q₁•Q₂•Q₃ •(Down)•CET
Mode Select Table
PE CEP CET
L
X
X
H
L
L
H
L
L
HH
X
HX
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Action on Rising
U/D
Clock Edge
X Load (P_n to Q_n)
H Count Up (Increment)
L Count Down (Decrement)
X No Change (Hold)
X No Change (Hold)
State Diagram
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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