FSQ0765RQ Datasheet, PDF (17/19 Pages) Fairchild Semiconductor – Green-Mode Fairchild Power Switch

PCB Layout Guide
Due to the combined scheme, FPS shows better noise
immunity than conventional PWM controller and
MOSFET discrete solution. Further more are internal
drain current sense eliminates the possibility of noise
generation caused by a sensing resistor. There are some
recommendations for PCB layout to enhance noise
immunity and suppress natural noise inevitable in power-
handling components.
There are typically two grounds in the conventional
SMPS: power ground and signal ground. The power
ground is the ground for primary input voltage and
power, while the signal ground is ground for PWM
controller. In FPS, those two grounds share the same
pin, GND. Normally the separate grounds do not share
the same trace and meet only at one point, the GND pin.
More, wider patterns for both grounds are good for large
currents by decreasing resistance.
Capacitors at the VCC and FB pins should be as close
as possible to the corresponding pins to avoid noise from
the switching device. Sometimes Mylar® or ceramic
capacitors with electrolytic for V_CC are better for smooth
operation. The ground of these capacitors needs to
connect to the signal ground (not power ground).
The cathode of the snubber diode should be close to the
drain pin to minimize stray inductance. The Y-capacitor
between primary and secondary should be directly
connected to the power ground of DC link to maximize
surge immunity.
Because the voltage range of feedback and sync line is
small, it is affected by the noise of the drain pin. Those
traces should not draw across or close to the drain line.
When the heat sink is connected to the ground, it should
be connected to the power ground. If possible, avoid
using jumper wires for power ground and drain.
Figure 37. Recommended PCB Layout
Mylar® is a registered trademark of DuPont Teijin Films.
© 2008 Fairchild Semiconductor Corporation
FSQ0765RQ Rev. 1.0.1
17
www.fairchildsemi.com