FAN7319 Datasheet, PDF (16/23 Pages) Fairchild Semiconductor – LCD Backlight Inverter Drive IC

Synchronous Drives
FAN7319 can be operated as zero current switching
(ZCS) or zero voltage switching (ZVS) mode using the
SENSE pin. Internal CT voltage is forced to discharge
when the SENSE pin voltage crosses the zero point. If
AC signal is applied to the SENSE pin, operating
frequency is synchronous with a frequency of input
signal. Figure 36 shows the synchronous operation in
push-pull topology.
During striking mode, the operating frequency is set to
fixed frequency by a resistor, regardless of the SENSE
pin zero crossing point.
The SENSE pin zero crossing frequency is faster than
set frequency. If zero crossing frequency is slower than
set frequency, frequency is abnormal due to irregular
discharging of CT voltage.
If SENSE zero crossing frequency is much faster than
set frequency, CT discharging voltage could be lower
than 1.5V. In this case, CT discharging voltage is held to
1.5V to prevent synchronous frequency being too high.
SENSE
2V
CT
CMP
0.5V
SYNC
T
OUTA
OUTB
Figure 36. Synchronous Operation in Push-Pull Mode
Protections
The FAN7319 provides the following latch-mode
protections: Open-Lamp Regulation (OLR), Open-Lamp
Protection (OLP), Short-Lamp Protection (SLP), CMP-
HIGH Protection, and Thermal Shutdown (TSD). The
latch is reset when VIN falls to the UVLO voltage or ENA
is pulled down to GND.
Protection timing can be calculated based on Figure 37.
Figure 37. Timer Charging Circuit
Assume that timer capacitor is 1µF.
Striking time is one-time charging from zero to 3V and
four-times charging from 0.3V to 3V with 2µA current
source. The striking time is calculated as follows:
t_strike
=
C∆V_str
I_sur1
= ^{1µF • 3V}
2µF
+ 4 • ^{1µF • 2.7V}
2µF
= 6.9s
(6)
The OVP and SLP delay times are calculated as:
t_OVP
_ SLP
=
C∆V_nor
I_{sur 2}
1µF • 1V
=
50µF
= 20ms
(7)
The CMP-HIGH protection and OLP delay times are
calculated as:
t_{OLP _ CMPH} =
C∆V_nor
I_sur1
1µF • 1V
=
2µF
= 500ms
(8)
Open-Lamp Regulation
When the maximum of the rectified OLR input voltages
V ^max is more than 3V, the IC enters regulation mode
OLR
and controls the CMP voltage. The IC limits the lamp
voltage by decreasing the CMP source current. If V ^max
OLR
is between 2V and 3V, the CMP source current
decreases from 40µA to 3µA. Then, if V ^max reaches
OLR
3V, CMP source current decreases to 0µA, so CMP
voltage remains constant and the lamp voltage also
remains constant, as shown in Figure 38. Finally, if
V ^max is more than 3.25V, the error amplifier for OLR is
OLR
operating and CMP sink current increases, so CMP
voltage decreases and the lamp voltage maintains the
determined value.
At the same time, while V ^max is more than OVPR, the
OLR
50µA current source starts charging TIMER capacitor in
normal mode. When TIMER voltage reaches 1V, the IC
enters shutdown, as shown in Figure 40. This protection
is disabled in striking mode to ignite lamps reliably.
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
16
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