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FSEZ1307 Datasheet, PDF (15/16 Pages) Fairchild Semiconductor – Primary-Side-Regulation PWM with Power MOSFET Integrated
Physical Dimensions
5.00
4.80
3.81
87
A
5
B
6.20
5.80
4.00
3.80
1.75
0.65
5.60
1
4
PIN ONE
INDICATOR
1.27
(0.33)
0.25 M C B A
1.27
LAND PATTERN RECOMMENDATION
0.25
0.10
1.75 MAX
C
SEE DETAIL A
0.25
0.19
R0.10
R0.10
8°
0°
0.90
0.406
0.51
0.33
0.10 C
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES:
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012 VARIATION AA EXCEPT FOR MISSING PIN 6.
SEATING PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
(1.04)
FLASH OR BURRS.
DETAIL A
D) DRAWING FILENAME: M07BREV2
SCALE: 2:1
Figure 34. 7-Lead, Small Outline Package (SOP-7)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FSEZ1307 • Rev. 1.0.2
15
www.fairchildsemi.com