FDMF6821B Datasheet, PDF (15/19 Pages) Fairchild Semiconductor – Extra-Small, High-Performance, High-Frequency DrMOS Module

Application Information
Supply Capacitor Selection
For the supply inputs (V_CIN), a local ceramic bypass
capacitor is recommended to reduce noise and to
supply the peak current. Use at least a 1 µF X7R or X5R
capacitor. Keep this capacitor close to the VCIN pin and
connect it to the GND plane with vias.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C_BOOT), as shown in Figure 30. A bootstrap capacitance
of 100 nF X7R or X5R capacitor is usually adequate. A
series bootstrap resistor may be needed for specific
applications to improve switching noise immunity. The
boot resistor may be required when operating above
15 V_IN and is effective at controlling the high-side
MOSFET turn-on slew rate and V_SHW overshoot. R_BOOT
values from 0.5 to 3.0 Ω are typically effective in
reducing VSWH overshoot.
V5V
A
I_{5V CVDRV}
R_VCIN
C_VCIN
VCIN Filter
The VDRV pin provides power to the gate drive of the
high-side and low-side power MOSFET. In most cases,
it can be connected directly to VCIN, the pin that
provides power to the logic section of the driver. For
additional noise immunity, an RC filter can be inserted
between the VDRV and VCIN pins. Recommended
values would be 10 Ω and 1 µF.
Power Loss and Efficiency
Measurement and Calculation
Refer to Figure 30 for power loss testing method.
Power loss calculations are:
P_IN=(V_IN x I_IN) + (V_5V x I_5V) (W)
(1)
P_SW=V_SW x I_OUT (W)
(2)
P_OUT=V_OUT x I_OUT (W)
(3)
P_{LOSS_MODULE}=P_IN - P_SW (W)
(4)
P_{LOSS_BOARD}=P_IN - P_OUT (W)
(5)
EFF_MODULE=100 x P_SW/P_IN (%)
(6)
EFF_BOARD=100 x P_OUT/P_IN (%)
(7)
A
V_IN
CVIN ^IIN
DISB#
PWM
Input
OFF
ON
Open -
Drain
Output
DISB#
VDRV
VCIN
PWM
FFDDMF678251B
SMOD#
THWN#
CGND
PGND
VIN
BOOT
VSWH
RBOOT
C_BOOT
PHASE
L_OUT
V V_SW
C_OUT
I OUT
A
V_OUT
V5V
DISB#
PWM
Input
OFF
ON
Open-
Drain
Output
Figure 29. Block Diagram With V_CIN Filter
A
I _5V
C_VDRV
A
V_IN
CVIN ^IIN
VDRV
VCIN
VIN
DISB#
PWM _{FFDDMMF68251B}
SMOD#
THWN#
CGND
PGND
BOOT
VSWH
RBOOT
CBOOT
PHASE
L_OUT
V VSW
COUT
I OUT
A
© 2012 Fairchild Semiconductor Corporation
FDMF6821B • Rev. 1.0.0
Figure 30. Power Loss Measurement
15
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