FDMF6705B Datasheet, PDF (15/19 Pages) Fairchild Semiconductor – Extra-Small, High-Performance, High- Frequency DrMOS Module

Application Information
Supply Capacitor Selection
For the supply inputs (VDRV and VCIN), a local ceramic
bypass capacitor is required to reduce noise and to
supply peak transient currents during gate drive
switching action. It is recommended to use a minimum
capacitor value of 1µF X7R or X5R. Keep this capacitor
close to the VCIN and VDRV pins and connect it to the
GND plane with vias.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C_BOOT), as shown in Figure 28. A bootstrap capacitance
of 100nF X7R or X5R capacitor is typically adequate. A
series bootstrap resistor may be needed for specific
applications to improve switching noise immunity. The
boot resistor (R_BOOT) may be required when operating
near the maximum rated V_IN and is effective at
controlling the high-side MOSFET turn-on slew rate and
VSHW overshoot. Typical R_BOOT values from 0.5 to 3.0Ω
are effective in reducing VSWH overshoot.
V5V
A
I5V _CVDRV
RVCIN
C_VCIN
VCIN Filter
The VDRV pin provides power to the gate drive of the
high-side and low-side power MOSFETs. In most cases,
VDRV can be connected directly to VCIN, which
supplies power to the logic circuitry of the gate driver.
For additional noise immunity, an RC filter can be
inserted between VDRV and VCIN. Recommended
values of 10Ω (R_VCIN) placed between VDRV and VCIN
and 1µF (C_VCIN) from VCIN to CGND, Figure 28.
Power Loss and Efficiency
Measurement and Calculation
Refer to Figure 29 for power-loss testing method. Power
loss calculations are:
P_IN=(V_IN x I_IN) + (V_5V x I_5V) (W)
(1)
P_SW=V_SW x I_OUT (W)
(2)
P_OUT=V_OUT x I_OUT (W)
(3)
P_{LOSS_MODULE}=P_IN - P_SW (W)
(4)
P_{LOSS_BOARD}=P_IN - P_OUT (W)
(5)
EFF_MODULE=100 x P_SW/P_IN (%)
(6)
EFF_BOARD=100 x P_OUT/P_IN (%)
(7)
A
V_IN
CVIN ^IIN
DISB#
PWM
Input
OFF
ON
Open -
Drain
Output
DISB#
VDRV
VCIN
PWM
FFDDMF6677055B
SMOD#
THWN
CGND
PGND
VIN
BOOT
VSWH
RBOOT
CBOOT
PHASE
LOUT
V VSW
COUT
IOUT
A
V_OUT
V5V
DISB#
PWM
Input
OFF
ON
Open-
Drain
Output
Figure 28. Block Diagram with V_CIN Filter
A
I 5V
CVDRV
A
V_IN
CVIN ^IIN
VDRV
VCIN
VIN
DISB#
PWM
SMOD
THWN#
F_FD_DM_MF670₅5B
CGND
PGND
BOOT
VSWH
RBOOT
C_BOOT
PHASE
LOUT
V V_SW
C_OUT
IOUT
A
© 2011 Fairchild Semiconductor Corporation
FDMF6705B • Rev. 1.0.2
Figure 29. Power Loss Measurement
15
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