FAN4800AS Datasheet, PDF (15/19 Pages) Fairchild Semiconductor – PFC/PWM Controller Combination

Two-Level PFC Function
To improve the efficiency, the system can reduce PFC
switching loss at low line and light load by reducing the
PFC output voltage. The two-level PFC output of the
FAN4801S/02S can be programmable.
As Figure 27 shows, FAN4801S/02S detect the voltage
of VEA and VRMS pins to determine if the system
operates low line and light load. At the second-level
PFC, there is a current of 20µA through RF2 from the
FBPFC pin. The second-level PFC output voltage can
be calculated as.
Output
≅
R_F1 + R_{F 2}
R_{F 2}
× (2.5V
−
20μA × R_F2 )
(3)
For example, if the second-level PFC output voltage is
expected as 300V and normal voltage is 387V,
according to the equation, RF2 is 28kΩ RF1 is 4.3MΩ.
The programmable range of second level PFC output
voltage is 340V ~ 300V.
Figure 27. Two-Level PFC Scheme
Oscillator (RT/CT)
The oscillator frequency is determined by the values of
RT and CT, which determine the ramp and off-time of
the oscillator output clock:
f_{RT / CT}
=
1
t_{RT / CT} + t_DEAD
(4)
The dead time of the oscillator is derived from the
following equation:
t_{RT / CT}
= C_T
× R_T
×
ln
⎛
⎜⎝
VREF − 1
VREF − 3.8
⎞
⎟⎠
(5)
at VREF=7.5V and tRT/CT=CT x RT x 0.56.
The dead time of the oscillator is determined using:
t_DEAD
=
2.8V
7.78mA
×
C_T
= 360 ×C_T
(6)
The dead time is so small (tRT/CT>>tDEAD) that the
operating frequency can typically be approximated by:
f_{RT / CT}
=
1
t_{RT / CT}
(7)
Pulse Width Modulator (PWM)
The operation of the PWM section is straightforward,
but there are several points that should be noted.
Foremost among these is the inherent synchronization
of PWM with the PFC section of the device, from which
it also derives its basic timing. The PWM is capable of
current-mode or voltage-mode operation. In current-
mode applications, the PWM ramp (RAMP) is usually
derived directly from a current-sensing resistor or
current transformer in the primary side of the output
stage. It is thereby representative of the current flowing
in the converter’s output stage. ILIMIT, which provides
cycle-by-cycle current limiting, is typically connected to
RAMP in such applications. For voltage-mode
operation and certain specialized applications, RAMP
can be connected to a separate RC timing network to
generate a voltage ramp against which FBPWM is
compared. Under these conditions, the use of voltage
feedforward from the PFC bus can assist in line
regulation accuracy and response. As in current-mode
operation, the ILIMIT input is used for output stage over-
current protection. No voltage error amplifier is included
in the PWM stage, as this function is generally
performed on the output side of the PWM’s isolation
boundary. To facilitate the design of opto-coupler
feedback circuitry, an offset has been built into the
PWM’s RAMP input that allows FBPWM to command a
0% duty cycle for input voltages below typical 1.5V.
PWM Cycle-by-Cycle Current Limiter
The ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin exceed 1V, the output flip-flop is reset
by the clock pulse at the start of the next PWM power
cycle. When the ILIMIT triggers the cycle-by-cycle bi-cycle
current, it limits the PWM duty cycle mode and the power
dissipation is reduced during the dead-short condition.
V_IN OK Comparator
The VIN OK comparator monitors the DC output of the
PFC and inhibits the PWM if the voltage on FBPFC is
less than its nominal 2.4V. Once the voltage reaches
2.4V, which corresponds to the PFC output capacitor
being charged to its rated boost voltage, soft-start begins.
PWM Soft-Start (SS)
PWM startup is controlled by selection of the external
capacitor at soft-start. A current source of 10µA
supplies the charging current for the capacitor and
startup of the PWM begins at 1.5V.
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
15
www.fairchildsemi.com