FDMF6823B Datasheet, PDF (14/19 Pages) Fairchild Semiconductor – Extra-Small, High-Performance, High-Frequency DrMOS Module

Skip Mode (SMOD#)
The Skip Mode function allows for higher converter
efficiency when operated in light-load conditions. When
SMOD# is pulled LOW, the low-side MOSFET gate
signal is disabled (held LOW), preventing discharge of
the output capacitors as the filter inductor current
attempts reverse current flow – known as “Diode
Emulation” Mode.
When the SMOD# pin is pulled HIGH, the synchronous
buck converter works in Synchronous Mode. This mode
allows for gating on the Low Side MOSFET. When the
SMOD# pin is pulled LOW, the low-side MOSFET is
gated off. If the SMOD# pin is connected to the PWM
controller, the controller can actively enable or disable
SMOD# when the controller detects light-load condition
from output current sensing. Normally this pin is active
LOW. See Figure 28 for timing delays.
Table 2. SMOD# Logic
DISB#
PWM
SMOD#
GH
GL
0
X
X
0
0
1
3-State
X
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
Note:
4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low-side FET V_GS
response time to control diode emulation on a cycle-by-cycle basis.
SMOD#
V IH_PWM
PWM
GH
to
VSWH
V IL_PWM
90%
1 0%
V IL_SMOD
V IH_PWM
10%
V IH_SMOD
VSWH
2.2V
CCM
CCM
GL
90%
1.0V
10%
t_{PD_PHGLL}
t_{PD_PLGHL}
t_{D_DEADON}
t_{D_DEADOFF}
t_{PD_SLGLL}
t_{PD_PHGHH}
Delay from SMOD# going
LOW to LS VGS LOW
HS turn -on with SMOD# LOW
Figure 28. SMOD# Timing Diagram
DCM
V OUT
1 0%
t_{PD_SHGLH}
Delay from SMOD# going
HIGH to LS V_GS HIGH
© 2011 Fairchild Semiconductor Corporation
FDMF6823B • Rev. 1.0.2
14
www.fairchildsemi.com