FDMF6705V Datasheet, PDF (14/18 Pages) Fairchild Semiconductor – Extra-Small, High- Performance, High-Frequency DrMOS Module

Application Information
Supply Capacitor Selection
For the supply input (VDRV), a local ceramic bypass
capacitor is required to have regulator stable and to
reduce noise. For the regulator output on VCIN, another
local ceramic bypass capacitor is needed to supply the
peak power MOSFET low-side gate current and boot
capacitor charging current. Use at least a 1µF, X7R or
X5R capacitors. Keep these capacitors close to the
FDMF6705V VDRV and VCIN pin and connect them to
GND plane with vias. Do not tie VDRV and VCIN pins
each other.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBOOT), as shown in Figure 26. A bootstrap
capacitance of 100nF X7R or X5R capacitor is
adequate. A series bootstrap resistor would be needed
for specific applications to improve switching noise
immunity.
Power Loss and Efficiency
Measurement and Calculation
Refer to Figure 26 for power loss testing method. Power
loss calculations are:
PIN=(VIN x IIN) + (VDRV x IDRV) (W)
PSW=VSW x IOUT (W)
POUT=VOUT x IOUT (W)
PLOSS_MODULE=PIN - PSW (W)
PLOSS_BOARD=PIN - POUT (W)
EFFMODULE=100 x PSW/PIN (%)
EFFBOARD=100 x POUT/PIN (%)
VDRV
A
IDRV
CVDRV
CVCIN
A
V_IN
CVIN
IIN
DISB#
PWM Input
OFF
ON
Open-Drain
Output
VDRV
VCIN
VIN
DISB#
PW M
FDMF6705V
SMOD#
BOOT
VSW H
RBOOT
CBOOT
THW N
CGND
PGND
PHASE
V VSW
L_OUT
COUT
I_OUT
A
VOUT
Figure 26. Power Loss Measurement Block Diagram
© 2011 Fairchild Semiconductor Corporation
FDMF6705V • Rev. 1.0.1
14
www.fairchildsemi.com