FAN4800 Datasheet, PDF (14/20 Pages) Fairchild Semiconductor – Low Start-Up Current PFC/PWM Controller Combos

2.6 Generating V_CC
After turning on the FAN4800 at 13V, the operating volt-
age can vary from 10V to 17.9V. The threshold voltage of
the V_CC OVP comparator is 17.9V and its hysteresis is
1.5V. When V_CC reaches 17.9V, PFC OUT is LOW, and
the PWM section is not disturbed. There are two ways to
generate V_CC: use auxiliary power supply around 15V or
use bootstrap winding to self-bias the FAN4800 system.
The bootstrap winding can be either taped from the PFC
boost choke or from the transformer of the DC-to-DC
stage.
The ratio of the bootstrap’s winding transformer should
be set between 18V and 15V. A filter network is recom-
mended between V_CC (pin 13) and bootstrap winding.
The resistor of the filter can be set as:
R_FILTER × I_VCC ≈ 2V,
( ) I_VCC = I_OP + Q_PFCFET +Q_PWMFET × f_SW I_OP
= 2.5A (typ.)
(15)
If V_CC goes beyond 17.9V, the PFC gate (pin 12) drive
goes LOW and the PWM gate drive (pin 11) remains
working. The resistor’s value must be chosen to meet
the operating current requirement of the FAN4800 itself
(5mA, maximum) in addition to the current required by
the two gate driver outputs.
2.8 Leading/Trailing Modulation
Conventional PWM techniques employ trailing-edge
modulation, in which the switch turns on right after the
trailing edge of the system clock. The error amplifier out-
put is then compared with the modulating ramp up. The
effective duty cycle of the trailing edge modulation is
determined during the on-time of the switch. Figure 10
shows a typical trailing-edge control scheme.
In the case of leading-edge modulation, the switch is
turned off exactly at the leading edge of the system
clock. When the modulating ramp reaches the level of
the error amplifier output voltage, the switch is turned on.
The effective duty-cycle of the leading-edge modulation
is determined during off-time of the switch. Figure 11
shows a leading-edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and Switch 2 (SW2) turns on at the same instant to mini-
mize the momentary no-load period, thus lowering ripple
voltage generated by the switching action. With such
synchronized switching, the ripple voltage of the first
stage is reduced. Calculation and evaluation have shown
that the 120Hz component of the PFC’s output ripple
voltage can be reduced by as much as 30% using the
leading-edge modulation method.
2.7 Example
To obtain a desired V_BIAS voltage of 18V, a V_CC of 15V,
and the FAN4800 driving a total gate charge of 90nC at
100kHz (e.g. one IRF840 MOSFET and two IRF820
MOSFET), the gate driver current required is:
I_GATEDRIVE = 100kHz × 90nC = 9mA
(16)
R_BIAS
= ^{VBIAS − VCC}
I_CC + I_G
= ^{18V −15V}
5mA + 9mA
(17)
Choose R_BIAS = 214Ω
(18)
Bypass the FAN4800 locally with a 1.0μF ceramic capac-
itor. In most applications, an electrolytic capacitor of
between 47μF and 220μF is also required across the
part both for filtering and as a part of the start-up boot-
strap circuitry.
© 2005 Fairchild Semiconductor Corporation
FAN4800 Rev. 1.0.5
14
www.fairchildsemi.com