 English |
|
|
|
|
|
|
|
| FSBM15SL60 Datasheet, PDF (13/16 Pages) Fairchild Semiconductor – SPMTM (Smart Power Module) | |||
| |||
| ◁ |
CPU
5V-Line
100 â¦
RPF
4.7kâ¦
100 â¦
100 â¦
1nF
CPF
1nF
RPL
4.7kâ¦
R PH
4.7kâ¦
CPL
0.47nF
C PH
1.2nF
SPM
IN(UH), IN(VH) , IN(WH)
IN (UL) , IN (VL) , IN(WL)
VFO
COM
Note:
1) It would be recommended that by-pass capacitors for the gating input signals, IN(UL), IN(VL), IN(WL), IN(UH), IN(VH) and IN(WH) should be placed on the SPM pins
and on the both sides of CPU and SPM for the fault output signal, VFO, as close as possible.
2) The logic input is compatible with standard CMOS or LSTTL outputs.
3) RPLCPL/RPHCPH/RPFCPF coupling at each SPM input is recommended in order to prevent input/output signalsâ oscillation and it should be as close as possible to
each of SPM pins.
Fig. 12. Recommended CPU I/O Interface Circuit
These Values depend on PW M Control Algorithm
15V-Line
One-Leg Diagram of SPM
20â¦
DBS
33uF 0.1uF
Vcc VB
IN HO
COM VS
470uF
0.1uF
Vcc
IN OUT
COM
P
Inverter
Output
N
Note:
It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
Fig. 13. Recommended Bootstrap Operation Circuit and Parameters
©2003 Fairchild Semiconductor Corporation
Rev. C, August 2003
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese